15h.org - User contributions [en]

AMD Opteron 3200 and 3300 Series

2026-10-04T21:14:02Z

Chacha:

Processors in the [[AMD Opteron 3200 and 3300 Series]] were designed with the [[Bulldozer]] (3200 series) and [[Piledriver]] (3300 series) microarchitectures and are compatible with the [[Socket AM3+|AM3+ socket]].

====Opteron 3200-series "Zurich" (32 nm)====

* All models support: ''MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, SSE4a, IOMMU, NX bit, AMD64, AMD-V, AES, CLMUL, AVX, CVT16–F16C, XOP, FMA4.''
* All models support single socket configurations
* Memory support: Up to 4 DIMMs per socket
* Memory controller: Two channels of UDIMM, RDIMM up to DDR3-1866
* Die size: 315 mm2

{|class="wikitable" style="text-align:center;"
! rowspan="2" | Model Number || rowspan="2" | Step. || rowspan="2" | Cores || colspan="3" | Frequency (GHz) || colspan="2" | Cache || rowspan="2" | Multi || rowspan="2" | TDP (W)
|-
! Base || Full Load turbo || Half Load turbo || L2 || L3 (MB)
|-
| colspan="10" style="background:#096; color:white; text-align:left;"| '''B2, Four core, high-efficiency'''
|-
! style="text-align:left;" | 3250 HE
| rowspan="2" | B2 || rowspan="2" | 4 || 2.5 || 2.8 || 3.5 || rowspan="2" | 2 × 2 MB || rowspan="2" | 4 || 12.5–17.5× || rowspan="2" | 45
|-
! style="text-align:left;" | 3260 HE
| 2.7 || 3.0 || 3.7 || 13.5–18.5×
|-
| colspan="10" style="background:#096; color:white; text-align:left;"| '''B2, Eight core, high-efficiency'''
|-
! style="text-align:left;" | 3280
| B2 || 8 || 2.4 || 2.7 || 3.5 || 4 × 2 MB || 8 || 12–17.5× || 65
|}

====Opteron 3300-series "Delhi" (32 nm)====

* All models support: ''MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, SSE4a, NX bit, AMD64, AMD-V, AES, CLMUL, AVX, XOP, FMA3, FMA4, CVT16–F16C, Turbo Core 3.0.''
* All models support single socket configurations
* Memory support: Up to 4 DIMMs per socket
* Memory controller: Two channels of UDIMM, RDIMM up to DDR3-1866
* Die size: 315 mm2

{|class="wikitable" style="text-align:center;"
! rowspan="2" | Model Number || rowspan="2" | Step. || rowspan="2" | Cores || colspan="3" | Frequency (GHz) || colspan="2" | Cache || rowspan="2" | Multi || rowspan="2" | TDP (W)
|-
! Base || Full Load turbo || Half Load turbo || L2 || L3 (MB)
|-
| colspan="10" style="background:#096; color:white; text-align:left;"| '''C0, Four core, energy-efficient'''
|-
! style="text-align:left;" | 3320 EE
| C0 || 4 || 1.9 || 2.1 || 2.5 || 2 × 2 MB || 8 || 9.5–12.5× || 25
|-
| colspan="10" style="background:#096; color:white; text-align:left;"| '''C0, Four core, high-efficiency'''
|-
! style="text-align:left;" | 3350 HE
| C0 || 4 || 2.8 || 3.1 || 3.8 || 2 × 2 MB || 8 || 14–19× || 45
|-
| colspan="10" style="background:#096; color:white; text-align:left;"| '''C0, Eight core, high-efficiency'''
|-
! style="text-align:left;" | 3365
| rowspan="2" | C0 || rowspan="2" | 8 || 2.3 || 2.6 || 3.3 || rowspan="2" | 4 × 2 MB || rowspan="2" | 8 || 11.5–16.5× || rowspan="2" | 65
|-
! style="text-align:left;" | 3380
| 2.6 || 2.9 || 3.6 || 13–18×
|}

'''Official Source Code and Documentation'''
* [https://review.coreboot.org/c/coreboot/+/554 AGESA Source Code]
* [https://15h.org/images/f/f7/44065_Arch2008.pdf AGESA Interface Specification]
* [https://15h.org/images/b/be/42301_15h_Mod_00h-0Fh_BKDG.pdf BIOS and Kernel Developer's Guide]
* [https://15h.org/images/e/ee/49687_15h_Mod_00h-0Fh_Opteron_PDS.pdf Product Data Sheet]
* [https://15h.org/images/a/af/47414_15h_sw_opt_guide.pdf Software Optimization Guide]

AMD Opteron 6200 and 6300 Series

2026-10-04T21:00:22Z

Chacha:

Processors in the [[AMD Opteron 6200 and 6300 Series]] were designed with the [[Bulldozer]] (6200 series) and [[Piledriver]] (6300 series) microarchitectures and are compatible with the [[Socket G34|G34 socket]].

====Opteron 6200-series "Interlagos" (32 nm)====
* All models support: ''MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, SSE4a, NX bit, AMD64, AMD-V, AES, CLMUL, AVX, XOP, FMA4.''
* All models support two or four socket configurations
* Memory support: Up to 12 DIMMs per socket
* Memory controller: Four channels of Registered memory (UDIMM, RDIMM) up to DDR3-1600
* Interlagos models have 16 MB of L3 cache (2x8 MB) but only 14 MB is visible with the HT Assist feature activated using 2 MB as a directory cache.

{|class="wikitable" style="text-align:center;"
! rowspan="2" | Model Number || rowspan="2" | Step. || rowspan="2" | Cores || colspan="3" | Frequency
(GHz)
! colspan="2" | Cache || rowspan="2" | Multi || rowspan="2" | TDP
(W)
|-
! Base || Full Load turbo || Half Load turbo || L2 || L3
|-
| colspan="10" style="background:#096; color:white; text-align:left;"| '''B2, Quad core'''
|-
! style="text-align:left;" | 6204
| B2 || 4 || 3.3 || — || — || 2 × 2 MB || 2 × 8 MB || 16.5× || 115
|-
| colspan="10" style="background:#096; color:white; text-align:left;"| '''B2, Eight core'''
|-
! style="text-align:left;" | 6212
| rowspan="2" | B2 || rowspan="2" | 8 || 2.6 || 2.9 || 3.2 || rowspan="2" | 4 × 2 MB || rowspan="2" | 2 × 8 MB || 13–16× || rowspan="2" | 115
|-
! style="text-align:left;" | 6220
| 3.0 || 3.3 || 3.6 || 15–18×
|-
| colspan="10" style="background:#096; color:white; text-align:left;"| '''B2, Twelve core'''
|-
! style="text-align:left;" | 6234
| rowspan="2" | B2 || rowspan="2" | 12 || 2.4 || 2.7 || 3.0 || rowspan="2" | 6 × 2 MB || rowspan="2" | 2 × 8 MB || 12–15× || rowspan="2" | 115
|-
! style="text-align:left;" | 6238
| 2.6 || 2.9 || 3.2 || 13–16×
|-
| colspan="10" style="background:#096; color:white; text-align:left;"| '''B2, Twelve core, high-efficiency'''
|-
! style="text-align:left;" | 6230 HE
| B2 || 12 || 2.2 || 2.5 || 3.1 || 6 × 2 MB || 2 × 8 MB || 11–15.5× || 85
|-
| colspan="10" style="background:#096; color:white; text-align:left;"| '''B2, Sixteen core'''
|-
! style="text-align:left;" | 6272
| rowspan="9" | B2 || rowspan="9" | 16 || 2.1 || 2.4 || 3.0 || rowspan="9" | 8 × 2 MB || rowspan="9" | 2 × 8 MB || 10.5–15× || rowspan="5" | 115
|-
! style="text-align:left;" | 6274
| 2.2 || 2.5 || 3.1 || 11–15.5×
|-
! style="text-align:left;" | 6275 "Fangio"
| 2.3 || ? || rowspan="2" | 3.2 || 11–15.5×
|-
! style="text-align:left;" | 6276
| 2.3 || 2.6 || 11.5–16×
|-
! style="text-align:left;" | 6278
| 2.4 || 2.7 || rowspan="2" | 3.3 || 12–16.5×
|-
! style="text-align:left;" | 6282 SE
| 2.6 || 3.0 || 13-16.5× || rowspan="4" | 140
|-
! style="text-align:left;" | 6284 SE
| 2.7 || 3.1 || 3.4 || 13.5–17×
|-
! style="text-align:left;" | 6287 SE
| 2.8 || rowspan="2" | 3.2 || 3.5 || 14–17.5×
|-
! style="text-align:left;" | 6291 SE
| 3.0 || 4.0 || 14–17.5×
|-
| colspan="10" style="background:#096; color:white; text-align:left;"| '''B2, Sixteen core, high-efficiency'''
|-
! style="text-align:left;" | 6262 HE
| B2 || 16 || 1.6 || 2.1 || 2.9 || 8 × 2 MB || 2 × 8 MB || 8–14.5× || 85
|}

====Opteron 6300-series "Abu Dhabi" (32 nm)====
* All models support: ''MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, SSE4a, NX bit, AMD64, AMD-V, IOMMU, AES, CLMUL, AVX, BMI1 (Bit Manipulation Instructions 1), ABM (Advanced Bit Manipulation), TBM (Trailing Bit Manipulation instructions), XOP, FMA3, FMA4, CVT16–F16C, Turbo Core 2.0, EVP (Enhanced Virus Protection).''
* All models support two or four socket configurations
* Memory support: Up to 12 DIMMs per socket
* Memory controller: Four channels of Registered memory (UDIMM, RDIMM) up to DDR3-1866
* Abu Dhabi models have 16 MB of L3 cache (2x8 MB) but only 14 MB is visible with the HT Assist feature activated using 2 MB as a directory cache.
* Two new 6300 models code-named "Warsaw" were added in 2014 (6338P and 6370P) that operate at lower clock frequencies using less power.<ref name="tech report warsaw">{{cite web|last=Gasior |first=Geoff |url=http://techreport.com/news/25946/16-core-warsaw-cpus-added-to-opteron-lineup |title=16-core ''Warsaw'' CPUs added to Opteron lineup |publisher=The Tech Report | date=January 22, 2014 |access-date=January 15, 2015}}</ref>

{|class="wikitable" style="text-align:center;"
! rowspan="2" | Model Number || rowspan="2" | Step. || rowspan="2" | Cores || colspan="3" | Frequency
(GHz)
! colspan="2" | Cache || rowspan="2" | Multi || rowspan="2" | TDP
(W)
|-
! Base || Full Load turbo || Half Load turbo || L2 || L3
|-
| colspan="10" style="background:#096; color:white; text-align:left;"| '''C0, Quad core'''
|-
! style="text-align:left;" | 6308
| C0 || 4 || 3.5 || — || — || 2 × 2 MB || 2 × 8 MB || 17.5× || 115
|-
| colspan="10" style="background:#096; color:white; text-align:left;"| '''C0, Eight core'''
|-
! style="text-align:left;" | 6320
| rowspan="2" | C0 || rowspan="2" | 8 || 2.8 || 3.1 || 3.3 || rowspan="2" | 4 × 2 MB || rowspan="2" | 2 × 8 MB || 14–16.5× || rowspan="2" | 115
|-
! style="text-align:left;" | 6328
| 3.2 || 3.5 || 3.8 || 16–19×
|-
| colspan="10" style="background:#096; color:white; text-align:left;"| '''C0, Twelve core'''
|-
! style="text-align:left;" | 6338P
| rowspan="3" | C0 || rowspan="3" | 12 || 2.3 || 2.5 || 2.8 || rowspan="3" | 6 × 2 MB || rowspan="3" | 2 × 8 MB || 11.5–14× || 99
|-
! style="text-align:left;" | 6344
| 2.6 || 2.9 || 3.2 || 13–16× || rowspan="2" | 115
|-
! style="text-align:left;" | 6348
| 2.8 || 3.1 || 3.4 || 14–17×
|-
| colspan="10" style="background:#096; color:white; text-align:left;"| '''C0, Sixteen core'''
|-
! style="text-align:left;" | 6370P
| rowspan="5" | C0 || rowspan="5" | 16 || 2.0 || 2.2 || 2.5 || rowspan="5" | 8 × 2 MB || rowspan="5" | 2 × 8 MB || 10–12.5× || 99
|-
! style="text-align:left;" | 6376
| 2.3 || 2.6 || 3.2 || 11.5–16× || rowspan="3" | 115
|-
! style="text-align:left;" | 6378
| 2.4 || 2.7 || 3.3 || 12–16.5×
|-
! style="text-align:left;" | 6380
| 2.5 || 2.8 || 3.4 || 12.5–17×
|-
! style="text-align:left;" | 6386 SE
| 2.8 || 3.2 || 3.5 || 14-17.5× || 140
|-
| colspan="10" style="background:#096; color:white; text-align:left;"| '''C0, Sixteen core, high-efficiency'''
|-
! style="text-align:left;" | 6366 HE
| C0 || 16 || 1.8 || 2.3 || 3.1 || 8 × 2 MB || 2 × 8 MB || 9–15.5× || 85
|}

'''Official Source Code and Documentation'''
* [https://review.coreboot.org/c/coreboot/+/554 AGESA Source Code]
* [https://15h.org/images/f/f7/44065_Arch2008.pdf AGESA Interface Specification]
* [https://15h.org/images/b/be/42301_15h_Mod_00h-0Fh_BKDG.pdf BIOS and Kernel Developer's Guide]
* [https://15h.org/images/e/ee/49687_15h_Mod_00h-0Fh_Opteron_PDS.pdf Product Data Sheet]
* [https://15h.org/images/a/af/47414_15h_sw_opt_guide.pdf Software Optimization Guide]

'''Reverse Engineering and Analysis'''
* [https://15h.org/images/a/ab/2014_paper_microcode.pdf Security Analysis of x86 Processor Microcode]

AMD Opteron 6200 and 6300 Series

2026-10-04T20:58:38Z

Chacha: Copied from https://en.wikipedia.org/wiki/List_of_AMD_Opteron_processors - CC BY-SA 4.0

Processors in the [[AMD Opteron 6200 and 6300 Series]] were designed with the [[Bulldozer]] (6200 series) and [[Piledriver]] (6300 series) microarchitectures and are compatible with the [[Socket G34|G34 socket]].

====Opteron 6200-series "Interlagos" (32 nm)====
AMD Opteron 6212 die
* All models support: ''MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, SSE4a, NX bit, AMD64, AMD-V, AES, CLMUL, AVX, XOP, FMA4.''
* All models support two or four socket configurations
* Memory support: Up to 12 DIMMs per socket
* Memory controller: Four channels of Registered memory (UDIMM, RDIMM) up to DDR3-1600
* Interlagos models have 16 MB of L3 cache (2x8 MB) but only 14 MB is visible with the HT Assist feature activated using 2 MB as a directory cache.

{|class="wikitable" style="text-align:center;"
! rowspan="2" | Model Number || rowspan="2" | Step. || rowspan="2" | Cores || colspan="3" | Frequency
(GHz)
! colspan="2" | Cache || rowspan="2" | Multi || rowspan="2" | TDP
(W)
|-
! Base || Full Load turbo || Half Load turbo || L2 || L3
|-
| colspan="10" style="background:#096; color:white; text-align:left;"| '''B2, Quad core'''
|-
! style="text-align:left;" | 6204
| B2 || 4 || 3.3 || — || — || 2 × 2 MB || 2 × 8 MB || 16.5× || 115
|-
| colspan="10" style="background:#096; color:white; text-align:left;"| '''B2, Eight core'''
|-
! style="text-align:left;" | 6212
| rowspan="2" | B2 || rowspan="2" | 8 || 2.6 || 2.9 || 3.2 || rowspan="2" | 4 × 2 MB || rowspan="2" | 2 × 8 MB || 13–16× || rowspan="2" | 115
|-
! style="text-align:left;" | 6220
| 3.0 || 3.3 || 3.6 || 15–18×
|-
| colspan="10" style="background:#096; color:white; text-align:left;"| '''B2, Twelve core'''
|-
! style="text-align:left;" | 6234
| rowspan="2" | B2 || rowspan="2" | 12 || 2.4 || 2.7 || 3.0 || rowspan="2" | 6 × 2 MB || rowspan="2" | 2 × 8 MB || 12–15× || rowspan="2" | 115
|-
! style="text-align:left;" | 6238
| 2.6 || 2.9 || 3.2 || 13–16×
|-
| colspan="10" style="background:#096; color:white; text-align:left;"| '''B2, Twelve core, high-efficiency'''
|-
! style="text-align:left;" | 6230 HE
| B2 || 12 || 2.2 || 2.5 || 3.1 || 6 × 2 MB || 2 × 8 MB || 11–15.5× || 85
|-
| colspan="10" style="background:#096; color:white; text-align:left;"| '''B2, Sixteen core'''
|-
! style="text-align:left;" | 6272
| rowspan="9" | B2 || rowspan="9" | 16 || 2.1 || 2.4 || 3.0 || rowspan="9" | 8 × 2 MB || rowspan="9" | 2 × 8 MB || 10.5–15× || rowspan="5" | 115
|-
! style="text-align:left;" | 6274
| 2.2 || 2.5 || 3.1 || 11–15.5×
|-
! style="text-align:left;" | 6275 "Fangio"
| 2.3 || ? || rowspan="2" | 3.2 || 11–15.5×
|-
! style="text-align:left;" | 6276
| 2.3 || 2.6 || 11.5–16×
|-
! style="text-align:left;" | 6278
| 2.4 || 2.7 || rowspan="2" | 3.3 || 12–16.5×
|-
! style="text-align:left;" | 6282 SE
| 2.6 || 3.0 || 13-16.5× || rowspan="4" | 140
|-
! style="text-align:left;" | 6284 SE
| 2.7 || 3.1 || 3.4 || 13.5–17×
|-
! style="text-align:left;" | 6287 SE
| 2.8 || rowspan="2" | 3.2 || 3.5 || 14–17.5×
|-
! style="text-align:left;" | 6291 SE
| 3.0 || 4.0 || 14–17.5×
|-
| colspan="10" style="background:#096; color:white; text-align:left;"| '''B2, Sixteen core, high-efficiency'''
|-
! style="text-align:left;" | 6262 HE
| B2 || 16 || 1.6 || 2.1 || 2.9 || 8 × 2 MB || 2 × 8 MB || 8–14.5× || 85
|}

====Opteron 6300-series "Abu Dhabi" (32 nm)====
* All models support: ''MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, SSE4a, NX bit, AMD64, AMD-V, IOMMU, AES, CLMUL, AVX, BMI1 (Bit Manipulation Instructions 1), ABM (Advanced Bit Manipulation), TBM (Trailing Bit Manipulation instructions), XOP, FMA3, FMA4, CVT16–F16C, Turbo Core 2.0, EVP (Enhanced Virus Protection).''
* All models support two or four socket configurations
* Memory support: Up to 12 DIMMs per socket
* Memory controller: Four channels of Registered memory (UDIMM, RDIMM) up to DDR3-1866
* Abu Dhabi models have 16 MB of L3 cache (2x8 MB) but only 14 MB is visible with the HT Assist feature activated using 2 MB as a directory cache.
* Two new 6300 models code-named "Warsaw" were added in 2014 (6338P and 6370P) that operate at lower clock frequencies using less power.<ref name="tech report warsaw">{{cite web|last=Gasior |first=Geoff |url=http://techreport.com/news/25946/16-core-warsaw-cpus-added-to-opteron-lineup |title=16-core ''Warsaw'' CPUs added to Opteron lineup |publisher=The Tech Report | date=January 22, 2014 |access-date=January 15, 2015}}</ref>

{|class="wikitable" style="text-align:center;"
! rowspan="2" | Model Number || rowspan="2" | Step. || rowspan="2" | Cores || colspan="3" | Frequency
(GHz)
! colspan="2" | Cache || rowspan="2" | Multi || rowspan="2" | TDP
(W)
|-
! Base || Full Load turbo || Half Load turbo || L2 || L3
|-
| colspan="10" style="background:#096; color:white; text-align:left;"| '''C0, Quad core'''
|-
! style="text-align:left;" | 6308
| C0 || 4 || 3.5 || — || — || 2 × 2 MB || 2 × 8 MB || 17.5× || 115
|-
| colspan="10" style="background:#096; color:white; text-align:left;"| '''C0, Eight core'''
|-
! style="text-align:left;" | 6320
| rowspan="2" | C0 || rowspan="2" | 8 || 2.8 || 3.1 || 3.3 || rowspan="2" | 4 × 2 MB || rowspan="2" | 2 × 8 MB || 14–16.5× || rowspan="2" | 115
|-
! style="text-align:left;" | 6328
| 3.2 || 3.5 || 3.8 || 16–19×
|-
| colspan="10" style="background:#096; color:white; text-align:left;"| '''C0, Twelve core'''
|-
! style="text-align:left;" | 6338P
| rowspan="3" | C0 || rowspan="3" | 12 || 2.3 || 2.5 || 2.8 || rowspan="3" | 6 × 2 MB || rowspan="3" | 2 × 8 MB || 11.5–14× || 99
|-
! style="text-align:left;" | 6344
| 2.6 || 2.9 || 3.2 || 13–16× || rowspan="2" | 115
|-
! style="text-align:left;" | 6348
| 2.8 || 3.1 || 3.4 || 14–17×
|-
| colspan="10" style="background:#096; color:white; text-align:left;"| '''C0, Sixteen core'''
|-
! style="text-align:left;" | 6370P
| rowspan="5" | C0 || rowspan="5" | 16 || 2.0 || 2.2 || 2.5 || rowspan="5" | 8 × 2 MB || rowspan="5" | 2 × 8 MB || 10–12.5× || 99
|-
! style="text-align:left;" | 6376
| 2.3 || 2.6 || 3.2 || 11.5–16× || rowspan="3" | 115
|-
! style="text-align:left;" | 6378
| 2.4 || 2.7 || 3.3 || 12–16.5×
|-
! style="text-align:left;" | 6380
| 2.5 || 2.8 || 3.4 || 12.5–17×
|-
! style="text-align:left;" | 6386 SE
| 2.8 || 3.2 || 3.5 || 14-17.5× || 140
|-
| colspan="10" style="background:#096; color:white; text-align:left;"| '''C0, Sixteen core, high-efficiency'''
|-
! style="text-align:left;" | 6366 HE
| C0 || 16 || 1.8 || 2.3 || 3.1 || 8 × 2 MB || 2 × 8 MB || 9–15.5× || 85
|}

'''Official Source Code and Documentation'''
* [https://review.coreboot.org/c/coreboot/+/554 AGESA Source Code]
* [https://15h.org/images/f/f7/44065_Arch2008.pdf AGESA Interface Specification]
* [https://15h.org/images/b/be/42301_15h_Mod_00h-0Fh_BKDG.pdf BIOS and Kernel Developer's Guide]
* [https://15h.org/images/e/ee/49687_15h_Mod_00h-0Fh_Opteron_PDS.pdf Product Data Sheet]
* [https://15h.org/images/a/af/47414_15h_sw_opt_guide.pdf Software Optimization Guide]

'''Reverse Engineering and Analysis'''
* [https://15h.org/images/a/ab/2014_paper_microcode.pdf Security Analysis of x86 Processor Microcode]

AMD Opteron 4200 and 4300 Series

2026-10-04T20:40:46Z

Chacha: Copied from https://en.wikipedia.org/wiki/List_of_AMD_Opteron_processors - CC BY-SA 4.0

Processors in the [[AMD Opteron 4200 and 4300 Series]] were designed with the [[Bulldozer]] (4200 series) and [[Piledriver]] (4300 series) microarchitectures and are compatible with the [[Socket C32|C32 socket]].

====Opteron 4200-series "Valencia" (32 nm)====
* All models support: ''MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, SSE4a, NX bit, AMD64, AMD-V, AES, CLMUL, AVX, XOP, FMA4.''
* All models support up to two socket configurations
* Memory support: Up to 4 DIMMs per socket
* Memory controller: Two channels of Registered memory (UDIMM, RDIMM) up to DDR3-1600

{|class="wikitable" style="text-align:center;"
! rowspan="2" | Model Number || rowspan="2" | Step. || rowspan="2" | Cores || colspan="3" | Frequency
(GHz)
! colspan="2" | Cache || rowspan="2" | Multi || rowspan="2" | TDP
(W)
|-
! Base || Full Load turbo || Half Load turbo || L2 || L3
(MB)
|-
| colspan="10" style="background:#096; color:white; text-align:left;"| '''B2, Quad core, energy-efficient'''
|-
! style="text-align:left;" | 42DX EE
| B2 || 4 || 2.2 || || 3.3 || 2 × 2 MB || 8 || 11–16.5× || 40
|-
| colspan="10" style="background:#096; color:white; text-align:left;"| '''B2, Six core'''
|-
! style="text-align:left;" | 4226
| rowspan="4" | B2 || rowspan="4" | 6 || 2.7 || 2.9 || 3.1 || rowspan="4" | 3 × 2 MB || rowspan="4" | 8 || 13.5–15.5× || rowspan="4" | 95
|-
! style="text-align:left;" | 4234
| 3.1 || 3.3 || 3.5 || 15.5–17.5×
|-
! style="text-align:left;" | 4238
| 3.3 || 3.5 || 3.7 || 16.5–18.5×
|-
! style="text-align:left;" | 4240
| 3.4 || 3.6 || 3.8 || 17–19×
|-
| colspan="10" style="background:#096; color:white; text-align:left;"| '''B2, Six core, high-efficiency'''
|-
! style="text-align:left;" | 4228 HE
| rowspan="2" | B2 || rowspan="2" | 6 || 2.8 || 3.1 || 3.6 || rowspan="2" | 3 × 2 MB || rowspan="2" | 8 || 14–18× || rowspan="2" | 65
|-
! style="text-align:left;" | 4230 HE
| 2.9 || 3.2 || 3.7 || 14.5–18.5×
|-
| colspan="10" style="background:#096; color:white; text-align:left;"| '''B2, Eight core'''
|-
! style="text-align:left;" | 4280
| rowspan="2" | B2 || rowspan="2" | 8 || 2.8 || 3.1 || 3.5 || rowspan="2" | 4 × 2 MB || rowspan="2" | 8 || 14–17.5× || rowspan="2" | 95
|-
! style="text-align:left;" | 4284
| 3.0 || 3.3 || 3.7 || 15–18.5×
|-
| colspan="10" style="background:#096; color:white; text-align:left;"| '''B2, Eight core, high-efficiency'''
|-
! style="text-align:left;" | 42MX HE
| rowspan="3" | B2 || rowspan="3" | 8 || 2.2 || || 3.3 || rowspan="3" | 4 × 2 MB || rowspan="3" | 8 || 11–16.5× || rowspan="3" | 65
|-
! style="text-align:left;" | 4274 HE
| 2.5 || 2.8 || 3.5 || 12.5×-17.5×
|-
! style="text-align:left;" | 4276 HE
| 2.6 || 2.9 || 3.6 || 13–18×
|-
| colspan="10" style="background:#096; color:white; text-align:left;"| '''B2, Eight core, energy-efficient'''
|-
! style="text-align:left;" | 4256 EE
| B2 || 8 || 1.6 || 1.9 || 2.8 || 4 × 2 MB || 8 || 8–14× || 35
|}

====Opteron 4300-series "Seoul" (32 nm)====
* All models support: ''MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, SSE4a, NX bit, AMD64, AMD-V, AES, CLMUL, AVX, XOP, FMA3, FMA4, CVT16–F16C, AMD Turbo Core.''
* All models support up to two socket configurations
* Memory support: Up to 4 DIMMs per socket
* Memory controller: Two channels of Registered memory (UDIMM, RDIMM) up to DDR3-1866

{|class="wikitable" style="text-align:center;"
! rowspan="2" | Model Number || rowspan="2" | Step. || rowspan="2" | Cores || colspan="3" | Frequency
(GHz)
! colspan="2" | Cache || rowspan="2" | Multi || rowspan="2" | TDP
(W)
|-
! Base || Full Load turbo || Half Load turbo || L2 || L3
(MB)
|-
| colspan="10" style="background:#096; color:white; text-align:left;"| '''C0, Quad core, energy-efficient'''
|-
! style="text-align:left;" | 43CX EE
| rowspan="2" | C0 || rowspan="2" | 4 || rowspan="2" | 2.2 || rowspan="2" | || rowspan="2" | 3.0 || rowspan="2" | 2 × 2 MB || rowspan="2" | 8 || rowspan="2" | 11–15× || rowspan="2" | 35
|-
! style="text-align:left;" | 4310 EE
|-
| colspan="10" style="background:#096; color:white; text-align:left;"| '''C0, Six core'''
|-
! style="text-align:left;" | 4334
| rowspan="2" | C0 || rowspan="2" | 6 || 3.1 || 3.3 || 3.5 || rowspan="2" | 3 × 2 MB || rowspan="2" | 8 || 15.5–17.5× || rowspan="2" | 95
|-
! style="text-align:left;" | 4340
| 3.5 || 3.7 || 3.8 || 17.5–19×
|-
| colspan="10" style="background:#096; color:white; text-align:left;"| '''C0, Six core, high-efficiency'''
|-
! style="text-align:left;" | 4332 HE
| C0 || 6 || 3.0 || 3.3 || 3.7 || 3 × 2 MB || 8 || 15–18.5× || 65
|-
| colspan="10" style="background:#096; color:white; text-align:left;"| '''C0, Eight core'''
|-
! style="text-align:left;" | 4386
| C0 || 8 || 3.1 || 3.4 || 3.8 || 4 × 2 MB || 8 || 15.5–19× || 95
|-
| colspan="10" style="background:#096; color:white; text-align:left;"| '''C0, Eight core, energy-efficient'''
|-
! style="text-align:left;" | 4365 EE
| C0 || 8 || 2.0 || 2.3 || 2.8 || 4 × 2 MB || 8 || 10–14× || 40
|-
| colspan="10" style="background:#096; color:white; text-align:left;"| '''C0, Eight core, high-efficiency'''
|-
! style="text-align:left;" | 43GK HE
| rowspan="2" | C0 || rowspan="2" | 8 || rowspan="2" | 2.6 || rowspan="2" | 2.9 || rowspan="2" | 3.6 || rowspan="2" | 4 × 2 MB || rowspan="2" | 8 || rowspan="2" | 13–18× || rowspan="2" | 65
|-
! style="text-align:left;" | 4376 HE
|}

'''Official Source Code and Documentation'''
* [https://review.coreboot.org/c/coreboot/+/554 AGESA Source Code]
* [https://15h.org/images/f/f7/44065_Arch2008.pdf AGESA Interface Specification]
* [https://15h.org/images/b/be/42301_15h_Mod_00h-0Fh_BKDG.pdf BIOS and Kernel Developer's Guide]
* [https://15h.org/images/e/ee/49687_15h_Mod_00h-0Fh_Opteron_PDS.pdf Product Data Sheet]
* [https://15h.org/images/a/af/47414_15h_sw_opt_guide.pdf Software Optimization Guide]

AMD Opteron 3200 and 3300 Series

2026-10-04T19:50:50Z

Chacha: Copied from https://en.wikipedia.org/wiki/List_of_AMD_Opteron_processors - CC BY-SA 4.0

Processors in the [[AMD Opteron 3200 and 3300 Series]] were designed with the [[Bulldozer]] (3200 series) and [[Piledriver]] (3300 series) microarchitectures and are compatible with the [[Socket AM3+|AM3+ socket]].

====Opteron 3200-series "Zurich" (32 nm)====

* All models support: ''MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, SSE4a, IOMMU, NX bit, AMD64, AMD-V, AES, CLMUL, AVX, CVT16–F16C, XOP, FMA4.''
* All models support single socket configurations
* Memory support: Up to 4 DIMMs per socket
* Memory controller: Two channels of UDIMM, RDIMM up to DDR3-1866
* Die size: 315 mm2

{|class="wikitable" style="text-align:center;"
! rowspan="2" | Model Number || rowspan="2" | Step. || rowspan="2" | Cores || colspan="3" | Frequency (GHz) || colspan="2" | Cache || rowspan="2" | Multi || rowspan="2" | TDP (W) || rowspan="2" | Socket
|-
! Base || Full Load turbo || Half Load turbo || L2 || L3 (MB)
|-
| colspan="11" style="background:#096; color:white; text-align:left;"| '''B2, Four core, high-efficiency'''
|-
! style="text-align:left;" | 3250 HE
| rowspan="2" | B2 || rowspan="2" | 4 || 2.5 || 2.8 || 3.5 || rowspan="2" | 2 × 2 MB || rowspan="2" | 4 || 12.5–17.5× || rowspan="2" | 45 || rowspan="2" | AM3+
|-
! style="text-align:left;" | 3260 HE
| 2.7 || 3.0 || 3.7 || 13.5–18.5×
|-
| colspan="11" style="background:#096; color:white; text-align:left;"| '''B2, Eight core, high-efficiency'''
|-
! style="text-align:left;" | 3280
| B2 || 8 || 2.4 || 2.7 || 3.5 || 4 × 2 MB || 8 || 12–17.5× || 65 || AM3+
|}

====Opteron 3300-series "Delhi" (32 nm)====

* All models support: ''MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, SSE4a, NX bit, AMD64, AMD-V, AES, CLMUL, AVX, XOP, FMA3, FMA4, CVT16–F16C, Turbo Core 3.0., ECC''
* All models support single socket configurations
* Memory support: Up to 4 DIMMs per socket
* Memory controller: Two channels of UDIMM, RDIMM up to DDR3-1866
* Die size: 315 mm2

{|class="wikitable" style="text-align:center;"
! rowspan="2" | Model Number || rowspan="2" | Step. || rowspan="2" | Cores || colspan="3" | Frequency (GHz) || colspan="2" | Cache || rowspan="2" | Multi || rowspan="2" | TDP (W) || rowspan="2" | Socket
|-
! Base || Full Load turbo || Half Load turbo || L2 || L3 (MB)
|-
| colspan="11" style="background:#096; color:white; text-align:left;"| '''C0, Four core, energy-efficient'''
|-
! style="text-align:left;" | 3320 EE
| C0 || 4 || 1.9 || 2.1 || 2.5 || 2 × 2 MB || 8 || 9.5–12.5× || 25 || AM3+
|-
| colspan="11" style="background:#096; color:white; text-align:left;"| '''C0, Four core, high-efficiency'''
|-
! style="text-align:left;" | 3350 HE
| C0 || 4 || 2.8 || 3.1 || 3.8 || 2 × 2 MB || 8 || 14–19× || 45 || AM3+
|-
| colspan="11" style="background:#096; color:white; text-align:left;"| '''C0, Eight core, high-efficiency'''
|-
! style="text-align:left;" | 3365
| rowspan="2" | C0 || rowspan="2" | 8 || 2.3 || 2.6 || 3.3 || rowspan="2" | 4 × 2 MB || rowspan="2" | 8 || 11.5–16.5× || rowspan="2" | 65 || rowspan="2" | AM3+
|-
! style="text-align:left;" | 3380
| 2.6 || 2.9 || 3.6 || 13–18×
|}

'''Official Source Code and Documentation'''
* [https://review.coreboot.org/c/coreboot/+/554 AGESA Source Code]
* [https://15h.org/images/f/f7/44065_Arch2008.pdf AGESA Interface Specification]
* [https://15h.org/images/b/be/42301_15h_Mod_00h-0Fh_BKDG.pdf BIOS and Kernel Developer's Guide]
* [https://15h.org/images/e/ee/49687_15h_Mod_00h-0Fh_Opteron_PDS.pdf Product Data Sheet]
* [https://15h.org/images/a/af/47414_15h_sw_opt_guide.pdf Software Optimization Guide]

Supermicro H8QG6

2026-09-25T06:00:18Z

Chacha: The image was corrected.

{{Infobox motherboard
|image = H8QGi+-F Motherboard.png
|image_size = 300

|manufacturer = [[Supermicro]]

|socket = 4x [[G34]]
|northbridge = AMD SR5690
|southbridge = AMD SP5100
|superio = Winbond W83527DHG-P
|bmc = [[Nuvoton WPCM450]]
|bmcflash = Onboard
|ram = 32 slots (4 channels) DDR3-1600 ECC RDIMM/UDIMM, up to 1024GB
|bios = 2 MiB soldered SOIC-8 (W25Q16V)
|formfactor = SWTX
|power = 2x 8-pin EPS

|slot1 = PCIe Gen2 x16

|gpu = Matrox G200eW
|nic = 2x Intel 82576 Gigabit
|storagecontroller = SP5100's SATA2 (3.0 Gbps)
|usbcontroller = SP5100's onboard USB 2.0
|serial = One external, one internal
|audio = None
}}

The H8QG6 motherboard variants with one northbridge ('''H8QGi+-F''' and '''H8QG6+-F''') are highly supported by [[coreboot-15h]]. The H8QG6 motherboards have 4 [[G34]] sockets, each with 8 DIMM slots; supporting a maximum configuration of 64 cores and 1 TB of RAM. LRDIMM modules may bring the maximum memory up to 2 TB, but this has not been tested.

== Open Source Firmware ==
Open source firmware for the H8QG6 series is provided by [[coreboot-15h]] utilizing AMD's open source AGESA and CIMx releases for platform initialization.
=== coreboot-15h ===
{{Excerpt|Coreboot-15h|[[Supermicro H8QG6]]|hat=no|bold=1}}

=== Missing Features ===
* SeaBIOS does not respond to keyboards behind a USB hub.
* Hibernation and Suspend/Resume are unsupported.
* Opteron 6100 series CPUs are unsupported.
* Support for the onboard BMC is untested.

=== Flashing ===
[[File:H8QGi Flashchip Location.png|frameless|300x300px]]
[[File:H8QGi Flashchip Orientation.png|frameless|300x300px]]

To switch from the stock firmware to coreboot, [[External Flashing | external flashing]] is required. The flash chip is located below the circular CMOS battery slot. The circle marking the location of pin 1 is highlighted red in the above image. The circle is a subtle indentation on the chip that can be seen with the aid of a flashlight.

== Deployed Systems ==
* [[RAD02]]

== Motherboard Diagrams ==
[[File:H8QGi Diagram.png|frameless|400x400px]]
[[File:H8QGi BlockDiagram.png|frameless|400x400px]]

== Motherboard Components ==
=== Socket G34 ===
{{Excerpt|Socket G34|inline=yes|bold=yes}}
==== AMD Opteron 6100 Series ====
{{:AMD Opteron 6100 Series}}

==== AMD Opteron 6200 and 6300 Series ====
{{:AMD Opteron 6200 and 6300 Series}}

=== AMD SR5690 ===
{{Excerpt|AMD SR5690|inline=yes|bold=yes}}
=== AMD SR5670 ===
{{Excerpt|AMD SR5670|inline=yes|bold=yes}}
=== AMD SP5100 ===
{{Excerpt|AMD SP5100|inline=yes|bold=yes}}
=== Winbond W83627DHG-P ===
{{Excerpt|Winbond W83627DHG-P|hat=no}}
=== Nuvoton W83795G ===
{{Excerpt|Nuvoton W83795G/ADG|hat=no}}
=== Nuvoton WPCM450 ===
{{Excerpt|Nuvoton WPCM450|hat=no}}

== References ==

User:Chacha

2026-09-25T05:13:23Z

Chacha: First version of my user page.

I'm Chacha and I like Coreboot. I'll improve this page soon.

File:H8QGi BlockDiagram.png

2026-09-25T05:09:43Z

Chacha: Chacha uploaded a new version of File:H8QGi BlockDiagram.png