AMD SP5100: Difference between revisions
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The [[AMD SP5100]] is a versatile Southbridge designed to complement AMD's server Northbridges, integrating essential I/O, communication, and other features for advanced server platforms into a single device. <ref>https://theretroweb.com/chips/5699</ref> | |||
'''AMD Source Code and Documentation''' | '''AMD Source Code and Documentation''' | ||
* [https://review.coreboot.org/c/coreboot/+/560 CIMx Source Code] | * [https://review.coreboot.org/c/coreboot/+/560 CIMx Source Code] | ||
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* [[:File:AMD SP5100 Databook.pdf|Product Databook]] | * [[:File:AMD SP5100 Databook.pdf|Product Databook]] | ||
* [[:File:SP5100 Product Errata.pdf|Product Errata]] | * [[:File:SP5100 Product Errata.pdf|Product Errata]] | ||
== References == | |||
Revision as of 14:01, 31 March 2025
The AMD SP5100 is a versatile Southbridge designed to complement AMD's server Northbridges, integrating essential I/O, communication, and other features for advanced server platforms into a single device. [1]
AMD Source Code and Documentation
- CIMx Source Code
- BIOS Developer's Guide
- Register Reference Guide
- Register Programming Requirements
- Product Databook
- Product Errata