AMD SP5100: Difference between revisions
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The [[AMD SP5100]] is a versatile Southbridge designed to complement AMD's server Northbridges, integrating essential I/O, communication, and other features for advanced server platforms into a single device. <ref>https://theretroweb.com/chips/5699</ref> | The [[AMD SP5100]] is a versatile Southbridge designed to complement AMD's server Northbridges, integrating essential I/O, communication, and other features for advanced server platforms into a single device. <ref>https://theretroweb.com/chips/5699</ref> | ||
''' | '''Official Source Code and Documentation''' | ||
* [https://review.coreboot.org/c/coreboot/+/560 CIMx Source Code] | * [https://review.coreboot.org/c/coreboot/+/560 CIMx Source Code] | ||
* [[:File:AMD SP5100 BIOS Developer's Guide.pdf|BIOS Developer's Guide]] | * [[:File:AMD SP5100 BIOS Developer's Guide.pdf|BIOS Developer's Guide]] | ||
Revision as of 14:02, 31 March 2025
The AMD SP5100 is a versatile Southbridge designed to complement AMD's server Northbridges, integrating essential I/O, communication, and other features for advanced server platforms into a single device. [1]
Official Source Code and Documentation
- CIMx Source Code
- BIOS Developer's Guide
- Register Reference Guide
- Register Programming Requirements
- Product Databook
- Product Errata