Coreboot-fam15: Difference between revisions
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# Update the device tree to include the second northbridge (src/mainboard/supermicro/h8dgi/devicetree.cb) | # Update the device tree to include the second northbridge (src/mainboard/supermicro/h8dgi/devicetree.cb) | ||
=== IOMMU === | === IOMMU === | ||
Source code exists to enable the IOMMU (see the IOMMU_SUPPORT_DISABLE parameter). A buffer needs to be allocated and provided to the AGESA/CIMX code before the IOMMU code can be activated/tested. | |||
=== Additional Motherboards === | === Additional Motherboards === | ||
== Board Status == | == Board Status == |
Revision as of 14:59, 31 August 2024
coreboot-fam15 is a distribution of coreboot for AMD Family 15h hardware, developed by mrothfuss. This version of coreboot utilizes AMD's open source AGESA firmware found in coreboot-4.0. This older version of coreboot can be built by Debian 6. Recent CPU microcode updates and support for the H8DGI motherboard have been added to the codebase (https://github.com/mrothfuss/coreboot-fam15). The AGESA codebase is robust, development primarily involves adding/improving board configurations.
Development Roadmap
Hardware Monitor
There is partial support for the hardware monitor (fan control) in the H8QGI and H8SCM motherboards. The default values need to be improved and the reliability needs to be tested. The H8QGI board is recommended to tune these values as it has a working debugging console. According to documentation, the H8DGI motherboard uses the same hardware monitor; but for unknown reasons coreboot can not find the chip.
- Improve and validate fan control on the H8QGI motherboard
- Add support on the H8DGI motherboard
Secondary Northbridge
The H8DGI has 6 PCIe slots, including 3 x16 slots. However, two of these x16 slots are on the secondary northbridge which has not been activated.
- Test changing the "MAX_NB_COUNT" parameter to 2 (src/mainboard/supermicro/h8dgi/platform_cfg.h)
- Update the device tree to include the second northbridge (src/mainboard/supermicro/h8dgi/devicetree.cb)
IOMMU
Source code exists to enable the IOMMU (see the IOMMU_SUPPORT_DISABLE parameter). A buffer needs to be allocated and provided to the AGESA/CIMX code before the IOMMU code can be activated/tested.
Additional Motherboards
Board Status
Supermicro/H8DGI
Pros
- Stable with as much as 512GB of RAM (atlas)
- Has debugging output on the RS232 port
Cons
- The IOMMU has not been activated
- Secondary northbridge has not been activated, this disables 3 out of the 6 PCIe slots.
- The only active x16 PCIe slot is very close to CPU1; large CPU coolers will obstruct this slot and limit GPU support.
- No fan control or hardware monitor
- No open source BMC (the stock BMC can be disabled by a motherboard jumper)
- Blob required for onboard VGA
Supermicro/H8SCM
Pros
- Stable with as much as 128GB of RAM
- Fan control and hardware monitor are active (limited testing suggests fans only accelerate)
Cons
- No debugging output on the RS232 port
- The IOMMU has not been activated
- No open source BMC (the stock BMC can be disabled by a motherboard jumper)
- Blob required for onboard VGA
Supermicro/H8QGI
Pros
- Has debugging output on the RS232 port
- Fan control and hardware monitor are active (limited testing suggests fans only accelerate)
Cons
- The IOMMU has not been activated
- No open source BMC (the stock BMC can be disabled by a motherboard jumper)
- Blob required for onboard VGA
- Minimally tested
ASUS/KGPE-D16 and ASUS/KCMA-D8
- Initial ports for these boards have been added (develop branch)
- The boards boot and have debugging output on the RS232 port
- The KGPE-D16 passes raminit and executes a coreboot payload
- No video output yet, it is unknown if these ports can actually boot an OS.