AMD SR5670: Difference between revisions

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The [[AMD SR5670]], formerly known as RD870S, is a versatile system logic designed for the latest server/workstation platform, supporting AMD's next-generation CPUs. The chipset features 34 PCI Express® (PCIe®) lanes, with 30 lanes dedicated to external PCIe devices and 4 for the A-Link Express II interface to AMD's Southbridges like the [[SP5100]] (formerly SB700S). Utilizing HyperTransportTM 3 and PCIe Gen 2 technologies, the SR5670 offers high performance and reliability in a compact 29mm x 29mm package. <ref>https://theretroweb.com/chips/5697</ref>
The [[AMD SR5670]], formerly known as RD870S, is a versatile system logic designed for the latest server/workstation platform, supporting AMD's next-generation CPUs. The chipset features 34 PCI Express® (PCIe®) lanes, with 30 lanes dedicated to external PCIe devices and 4 for the A-Link Express II interface to AMD's Southbridges like the [[SP5100]] (formerly SB700S). Utilizing HyperTransportTM 3 and PCIe Gen 2 technologies, the SR5670 offers high performance and reliability in a compact 29mm x 29mm package. <ref>https://theretroweb.com/chips/5697</ref>


'''Official Source Code and Documentation'''
{{Excerpt|AMD SR56X0 Documentation|inline=yes|bold=yes}}
* [https://review.coreboot.org/c/coreboot/+/557 CIMx Source Code]
* [https://15h.org/images/c/c3/AMD_SR5690_5670_5650_BIOS_Developers_Guide.pdf BIOS Developer's Guide]
* [https://15h.org/images/2/24/48882-2.62.pdf IOMMU Specification]
* [https://15h.org/images/9/9a/AMD_SR5690_5670_5650_Register_Reference_Guide.pdf Register Reference Guide]
* [https://15h.org/images/b/b0/AMD_SR5690_5670_5650_Register_Programming_Requirements.pdf Register Programming Requirements]
* [https://15h.org/images/2/23/AMD_SR5670_Databook.pdf Product Databook]
* [https://15h.org/images/5/5d/SR56x0_Product_Errata.pdf Product Errata]
== References ==
== References ==

Revision as of 17:32, 16 October 2025

The AMD SR5670, formerly known as RD870S, is a versatile system logic designed for the latest server/workstation platform, supporting AMD's next-generation CPUs. The chipset features 34 PCI Express® (PCIe®) lanes, with 30 lanes dedicated to external PCIe devices and 4 for the A-Link Express II interface to AMD's Southbridges like the SP5100 (formerly SB700S). Utilizing HyperTransportTM 3 and PCIe Gen 2 technologies, the SR5670 offers high performance and reliability in a compact 29mm x 29mm package. [1]

Page 'AMD SR56X0 Documentation' not found

References

  1. ↑ https://theretroweb.com/chips/5697
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