AMD SR5650: Difference between revisions
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The [[AMD SR5650]], previously known as RD870S, is a powerful system logic designed for the server/workstation platform. The SR5650 boasts 26 PCI Express® (PCIe®) lanes, with 22 lanes dedicated to external PCIe devices and 4 for the A-Link Express II interface to AMD's Southbridges like the [[SP5100]] (formerly SB700S). The chipset is also equipped with the latest HyperTransportTM 3 and PCIe Gen 2 technologies, delivering exceptional performance in a compact 29mm x 29mm package.<ref>https://theretroweb.com/chips/5698</ref> | |||
'''AMD Source Code and Documentation''' | '''AMD Source Code and Documentation''' | ||
* [https://review.coreboot.org/c/coreboot/+/557 CIMx Source Code] | * [https://review.coreboot.org/c/coreboot/+/557 CIMx Source Code] | ||
Revision as of 13:59, 31 March 2025
The AMD SR5650, previously known as RD870S, is a powerful system logic designed for the server/workstation platform. The SR5650 boasts 26 PCI Express® (PCIe®) lanes, with 22 lanes dedicated to external PCIe devices and 4 for the A-Link Express II interface to AMD's Southbridges like the SP5100 (formerly SB700S). The chipset is also equipped with the latest HyperTransportTM 3 and PCIe Gen 2 technologies, delivering exceptional performance in a compact 29mm x 29mm package.[1]
AMD Source Code and Documentation