AMD SR5650: Difference between revisions
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* [[:File:AMD SR5650 Databook.pdf|Product Databook]] | * [[:File:AMD SR5650 Databook.pdf|Product Databook]] | ||
* [[:File:SR56x0 Product Errata.pdf|Product Errata]] | * [[:File:SR56x0 Product Errata.pdf|Product Errata]] | ||
== References == | |||
Revision as of 13:59, 31 March 2025
The AMD SR5650, previously known as RD870S, is a powerful system logic designed for the server/workstation platform. The SR5650 boasts 26 PCI Express® (PCIe®) lanes, with 22 lanes dedicated to external PCIe devices and 4 for the A-Link Express II interface to AMD's Southbridges like the SP5100 (formerly SB700S). The chipset is also equipped with the latest HyperTransportTM 3 and PCIe Gen 2 technologies, delivering exceptional performance in a compact 29mm x 29mm package.[1]
AMD Source Code and Documentation
- CIMx Source Code
- BIOS Developer's Guide
- Register Reference Guide
- Register Programming Requirements
- Product Databook
- Product Errata