AMD SR5650: Difference between revisions

From 15h.org
Jump to navigation Jump to search
No edit summary
No edit summary
Line 1: Line 1:
The [[AMD SR5650]], previously known as RD870S, is a powerful system logic designed for the server/workstation platform. The SR5650 boasts 26 PCI Express® (PCIe®) lanes, with 22 lanes dedicated to external PCIe devices and 4 for the A-Link Express II interface to AMD's Southbridges like the [[SP5100]] (formerly SB700S). The chipset is also equipped with the latest HyperTransportTM 3 and PCIe Gen 2 technologies, delivering exceptional performance in a compact 29mm x 29mm package.<ref>https://theretroweb.com/chips/5698</ref>
The [[AMD SR5650]], previously known as RD870S, is a powerful system logic designed for the server/workstation platform. The SR5650 boasts 26 PCI Express® (PCIe®) lanes, with 22 lanes dedicated to external PCIe devices and 4 for the A-Link Express II interface to AMD's Southbridges like the [[SP5100]] (formerly SB700S). The chipset is also equipped with the latest HyperTransportTM 3 and PCIe Gen 2 technologies, delivering exceptional performance in a compact 29mm x 29mm package.<ref>https://theretroweb.com/chips/5698</ref>


'''AMD Source Code and Documentation'''
'''Official Source Code and Documentation'''
* [https://review.coreboot.org/c/coreboot/+/557 CIMx Source Code]
* [https://review.coreboot.org/c/coreboot/+/557 CIMx Source Code]
* [[:File:AMD SR5690 5670 5650 BIOS Developers Guide.pdf|BIOS Developer's Guide]]
* [[:File:AMD SR5690 5670 5650 BIOS Developers Guide.pdf|BIOS Developer's Guide]]

Revision as of 14:02, 31 March 2025

The AMD SR5650, previously known as RD870S, is a powerful system logic designed for the server/workstation platform. The SR5650 boasts 26 PCI Express® (PCIe®) lanes, with 22 lanes dedicated to external PCIe devices and 4 for the A-Link Express II interface to AMD's Southbridges like the SP5100 (formerly SB700S). The chipset is also equipped with the latest HyperTransportTM 3 and PCIe Gen 2 technologies, delivering exceptional performance in a compact 29mm x 29mm package.[1]

Official Source Code and Documentation

References