K10

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K10
The "Thuban" CPU die used in Phenom II X6 and 8400-series Opteron models.
Overview
IntroducedSeptember 10, 2007
Process Node65 nm SOI, 45 nm SOI, 32 nm SOI @ GlobalFoundries
Microarchitectures
Chronology
PredecessorAMD K8 (Athlon 64)
SuccessorFamily 15h (Bulldozer, etc.)

The K10 microarchitecure (incorrectly known as "Family 10h", or ambiguously as "Stars") is a microarchitecture used for AMD x86-compatible CPUs in the period from years 2007 to 2013.

The K10 microarchitecture is comprised of two families:

In AMD’s early CPU microarchitecures, starting with the K5, the "K" was intended to mean "kryptonite", the only substance that can kill Superman, i.e. Intel.

ISA Extensions

Supported ISA extensions (AMD64):

  • SSE, SSE2, SSE3, SSE4a, ABM
  • Note: SSSE3 is NOT supported; also SSE4a is not the same as SSE4.1

Additional supported extensions in 32-bit mode:

  • MMX, Extended 3DNow!

Supported operating modes:

  • real mode (1 MiB addresses), (FreeDOS compatible)
  • x86-32, 32-bit protected mode
  • 64-bit mode / long mode (AMD64)

Virtualization support:

  • AMD-V
  • IOMMUv1 on selected chipsets.
  • no support for IOMMUv2, which accelerates nested IO virtualization

Memory Support

  • DDR2, usually UDIMM (depending on the motherboard), on the sockets:
  • DDR3, usually UDIMM (depending on the motherboard), on the sockets:

ECC Support:

  • On 32 nm (Llano): no ECC support at all.
  • On 45 nm dies: ECC UDIMM modules (also known as EUDIMM) are almost universally supported, but vendor BIOS/UEFI on many motherboards does not provide an option to enable it. In such cases, ECC can be enabled manually in Linux (the Linux module name is amd64_edac)

Sub-families

There are 3 major sub-families. The 45 nm dies group is the most extensive, as it is made of 3 different dies. The 65 nm dies group is a single die. The final die is 32 nm from Family 12h.

  • 65 nm dies: detailed article
    • Codename: Deer Hound
      • [AM2+] Agena B2/B3: Phenom X4, L3 = 2 MiB, B2 stepping 2007/11/19, B3 stepping 2008/03/27
      • [AM2+] Toliman B2/B3: Phenom X3, L3 = 2 MiB, harvested from Agena die, B2 stepping 2008/03/27, B3 stepping 2008/04/23
      • [AM2+] Kuma B3: Athlon X2, L3 = 2 MiB, harvested from Agena die
      • [Fr2] Barcelona BA, B3: Opteron quad-core (23xx, 83xx) 2360/8360 and below, released 2007/09/19, up to 2.5 GHz @ 95 W
      • [AM2+] Budapest: Opteron quad-core (13yy) 1356 and below
  • 45 nm dies: detailed article
    • Codenames: Pharaoh Hound, for Opterons: Hydra
      • [AM3] Thuban E0: Phenom II X6, L3 = 6 MiB, L2 = 512 KiB, E0 stepping 2010/04/27, up to 3.7 GHz @ 125 W
      • [AM3] Zosma E0: Phenom II X4, L3 = 6 MiB, L2 = 512 KiB, harvested from Thuban die, up to 3.5 GHz @ 125 W
      • [AM3] Zosma E0: Athlon II X4, L3 disabled, L2 = 512 KiB, harvested from Thuban die, up to 3.5 GHz @ 125 W
      • [Fr6] Istanbul D0: Opteron hexa-core (24xx, 84xx), D0 stepping, DDR2, 2009/06/01
      • [C32] Lisbon D0: Opteron quad-core (4122, 4130), D0 stepping 2010/06/23
      • [C32] Lisbon D1: Opteron hexa-core (4162 - 4184)
      • [G34] Magny-corus D1: Opteron with 8 cores MCM (6124 – 6140), D1 stepping 2010/03/29
      • [G34] Magny-corus D1: Opteron with 12 cores MCM (6164-6180SE), D1 stepping 2010/03/29
    • Codenames: Ridge Back, for AM3 Athlons: BL
      • [AM3] Deneb C2/C3: Phenom II X4, L3 = 6 MiB, L2 = 512 KiB, C2 stepping 2009/01/08, up to 3.7 GHz @ 95 W
      • [AM3] Heka C2/C3: Phenom II X3, L3 = 6 MiB, L2 = 512 KiB, harvested from Deneb die, C2 stepping 2009/02/09
      • [AM3] Rana C2/C3: Athlon II X3, L3 disabled, L2 = 512 KiB, harvested from Deneb die
      • [AM3] Propus C3: Phenom II X4, L3 disabled, L2 = 512 KiB, models 840 and 850, harvested from Deneb die
      • [AM3] Propus C2/C3: Athlon II X4, L3 disabled, L2 = 512 KiB, harvested from Deneb die
      • [mobile] Champlain C3: Phenom II (X4 or X3), L3 disabled, L2 = 512 KiB, harvested from Deneb die
      • [AM3] Callisto C2/C3: Phenom II X2, L3 = 6 MiB, L2 = 512 KiB, harvested from Deneb die, up to 3.5 GHz @ 80 W
      • [AM2+] C2: Athlon X2 (5000+/5200+), L3 disabled, L2 = 512 KiB, 65 W, harvested from Deneb die
      • [Fr2/Fr5] Shanghai C2: Opteron quad-core (23xx, 83xx) 2370/8370 and above, released 2009/01/26
      • [AM3] Suzuka C2: Opteron quad-core (13yy) 1381 and above, released 2009/04/22
    • Codename: Danube
      • [AM3] Regor C2/C3: Athlon II X2, 1 MiB L2, no L3
      • [AM3] Regor C3: Phenom II X2 (511 or 512), 1 MiB L2, no L3, up to 3.5 GHz @ 65 W
      • [AM3] Sargas C2/C3: Athlon II (single-core low-power), 1 MiB L2, no L3, up to 2.0 GHz @ 20 W
      • [mobile] Caspian: Turion II (mobile X2), no L3, Regor die
      • [mobile] Champlain: Turion II (mobile X2), Phenom II (mobile X2), no L3, Regor die
      • [mobile] Geneva: Turion II (mobile X2), no L3, Regor die
      • V-Series
  • 32 nm dies
    • Codename: Llano (Family 12h by CPUID, K10 microarchitecture)
      • [FM1] Lynx B0: Athlon X4 / X2, no L3, L2 = 512 KiB, integrated GPU, up to 3.0 GHz @ 100 W
      • [FS1] Sabine (mobile): A4, A6, A8 3000 Series, E2-3000M


Microcode

Microcode for K10 family is not encrypted, and it has been partially analyzed (see paper: Reverse Engineering x86 Processor Microcode[1]).

All microcodes released for later processor families are encrypted.[2]

See Also

References

  1. ↑ https://www.usenix.org/system/files/conference/usenixsecurity17/sec17-koppe.pdf
  2. ↑ https://www.dcddcc.com/docs/2014_paper_microcode.pdf
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