AMD SP5100: Difference between revisions
Jump to navigation
Jump to search
No edit summary |
No edit summary |
||
| Line 3: | Line 3: | ||
'''Official Source Code and Documentation''' | '''Official Source Code and Documentation''' | ||
* [https://review.coreboot.org/c/coreboot/+/560 CIMx Source Code] | * [https://review.coreboot.org/c/coreboot/+/560 CIMx Source Code] | ||
* [ | * [https://15h.org/images/a/ad/AMD_SP5100_BIOS_Developer%27s_Guide.pdf BIOS Developer's Guide] | ||
* [ | * [https://15h.org/images/7/78/AMD_SP5100_Register_Reference_Guide.pdf Register Reference Guide] | ||
* [ | * [https://15h.org/images/7/7b/AMD_SP5100_Register_Programming_Requirements.pdf Register Programming Requirements] | ||
* [ | * [https://15h.org/images/d/df/AMD_SP5100_Databook.pdf Product Databook] | ||
* [ | * [https://15h.org/images/e/ec/SP5100_Product_Errata.pdf Product Errata] | ||
== References == | == References == | ||
Latest revision as of 18:33, 31 March 2025
The AMD SP5100 is a versatile Southbridge designed to complement AMD's server Northbridges, integrating essential I/O, communication, and other features for advanced server platforms into a single device. [1]
Official Source Code and Documentation
- CIMx Source Code
- BIOS Developer's Guide
- Register Reference Guide
- Register Programming Requirements
- Product Databook
- Product Errata