AMD SP5100: Difference between revisions
Jump to navigation
Jump to search
No edit summary |
No edit summary |
||
| Line 8: | Line 8: | ||
* [https://15h.org/images/d/df/AMD_SP5100_Databook.pdf Product Databook] | * [https://15h.org/images/d/df/AMD_SP5100_Databook.pdf Product Databook] | ||
* [https://15h.org/images/e/ec/SP5100_Product_Errata.pdf Product Errata] | * [https://15h.org/images/e/ec/SP5100_Product_Errata.pdf Product Errata] | ||
== Block Diagrams == | |||
[[File:SP5100 BlockDiagram.png|frameless|400x400px]] | |||
== References == | == References == | ||
Revision as of 01:10, 21 September 2025
The AMD SP5100 is a versatile Southbridge designed to complement AMD's server Northbridges, integrating essential I/O, communication, and other features for advanced server platforms into a single device. [1]
Official Source Code and Documentation
- CIMx Source Code
- BIOS Developer's Guide
- Register Reference Guide
- Register Programming Requirements
- Product Databook
- Product Errata
Block Diagrams
