AMD SR5650: Difference between revisions
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The [[AMD SR5650]], previously known as RD870S, is a powerful system logic designed for the server/workstation platform. The SR5650 boasts 26 PCI Express® (PCIe®) lanes, with 22 lanes dedicated to external PCIe devices and 4 for the A-Link Express II interface to AMD's Southbridges like the [[SP5100]] (formerly SB700S). The chipset is also equipped with the latest HyperTransportTM 3 and PCIe Gen 2 technologies, delivering exceptional performance in a compact 29mm x 29mm package.<ref>https://theretroweb.com/chips/5698</ref> | The [[AMD SR5650]], previously known as RD870S, is a powerful system logic designed for the server/workstation platform. The SR5650 boasts 26 PCI Express® (PCIe®) lanes, with 22 lanes dedicated to external PCIe devices and 4 for the A-Link Express II interface to AMD's Southbridges like the [[SP5100]] (formerly SB700S). The chipset is also equipped with the latest HyperTransportTM 3 and PCIe Gen 2 technologies, delivering exceptional performance in a compact 29mm x 29mm package.<ref>https://theretroweb.com/chips/5698</ref> | ||
'''Official Source Code and Documentation''' | |||
* [https://review.coreboot.org/c/coreboot/+/557 CIMx Source Code] | |||
* [https://15h.org/images/c/c3/AMD_SR5690_5670_5650_BIOS_Developers_Guide.pdf BIOS Developer's Guide] | |||
* [https://15h.org/images/2/24/48882-2.62.pdf IOMMU Specification] | |||
* [https://15h.org/images/9/9a/AMD_SR5690_5670_5650_Register_Reference_Guide.pdf Register Reference Guide] | |||
* [https://15h.org/images/b/b0/AMD_SR5690_5670_5650_Register_Programming_Requirements.pdf Register Programming Requirements] | |||
* [https://15h.org/images/e/e4/AMD_SR5650_Databook.pdf Product Databook] | |||
* [https://15h.org/images/5/5d/SR56x0_Product_Errata.pdf Product Errata] | |||
== References == | == References == | ||
Latest revision as of 17:40, 16 October 2025
The AMD SR5650, previously known as RD870S, is a powerful system logic designed for the server/workstation platform. The SR5650 boasts 26 PCI Express® (PCIe®) lanes, with 22 lanes dedicated to external PCIe devices and 4 for the A-Link Express II interface to AMD's Southbridges like the SP5100 (formerly SB700S). The chipset is also equipped with the latest HyperTransportTM 3 and PCIe Gen 2 technologies, delivering exceptional performance in a compact 29mm x 29mm package.[1]
Official Source Code and Documentation
- CIMx Source Code
- BIOS Developer's Guide
- IOMMU Specification
- Register Reference Guide
- Register Programming Requirements
- Product Databook
- Product Errata