AMD SR5670: Difference between revisions
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* [https://15h.org/images/9/9a/AMD_SR5690_5670_5650_Register_Reference_Guide.pdf Register Reference Guide] | * [https://15h.org/images/9/9a/AMD_SR5690_5670_5650_Register_Reference_Guide.pdf Register Reference Guide] | ||
* [https://15h.org/images/b/b0/AMD_SR5690_5670_5650_Register_Programming_Requirements.pdf Register Programming Requirements] | * [https://15h.org/images/b/b0/AMD_SR5690_5670_5650_Register_Programming_Requirements.pdf Register Programming Requirements] | ||
* [https://15h.org/images/ | * [https://15h.org/images/2/23/AMD_SR5670_Databook.pdf Product Databook] | ||
* [https://15h.org/images/5/5d/SR56x0_Product_Errata.pdf Product Errata] | * [https://15h.org/images/5/5d/SR56x0_Product_Errata.pdf Product Errata] | ||
== References == | == References == | ||
Latest revision as of 01:35, 9 December 2025
The AMD SR5670, formerly known as RD870S, is a versatile system logic designed for the latest server/workstation platform, supporting AMD's next-generation CPUs. The chipset features 34 PCI Express® (PCIe®) lanes, with 30 lanes dedicated to external PCIe devices and 4 for the A-Link Express II interface to AMD's Southbridges like the SP5100 (formerly SB700S). Utilizing HyperTransportTM 3 and PCIe Gen 2 technologies, the SR5670 offers high performance and reliability in a compact 29mm x 29mm package. [1]
Official Source Code and Documentation
- CIMx Source Code
- BIOS Developer's Guide
- IOMMU Specification
- Register Reference Guide
- Register Programming Requirements
- Product Databook
- Product Errata