H8DGi

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H8DGi
Overview
IntroducedTBD
ManufacturerSuper Micro
Specifications
Socket2x G34
Northbridge2x AMD SR5690
SouthbridgeAMD SP5100
Super I/OWinbond W83527
BMCWinbond WPCM450 BMC
BMC Flash LocationOnboard Module
Memory16 slots (8 channels) DDR3-1600 ECC RDIMM/UDIMM, up to 512GB on coreboot
BIOS Flash2 MiB soldered
Form FactorE-ATX
Power Inputs2x 8-pin EPS
Expansion Slots
  • PCIe Gen2 x8 (electrically x4, NB2)
  • PCIe Gen2 x16 (NB2)
  • PCIe Gen2 x8 (NB1)
  • PCIe Gen2 x16 (NB2)
  • PCIe Gen2 x8 (electrically x4, NB1)
  • PCIe Gen2 x16 (NB1)
Onboard Peripherals
Graphics AdapterMatrox G200 16MB DDR2
Network Interface2x Intel 82576 Gigabit
Storage ControllerSP5100's SATA2 (3.0 Gbps)
USB ControllerSP5100's onboard USB 2.0
Serial InterfaceOne SIO-provided RS232
Audio InterfaceNone

The H8DGi motherboard is partially supported by coreboot-15h.

Board Variants

H8DGi

Release
Notes
Download Options
2025.05.03-v4.11-6656887228f
  • Initial support
    • No fan control
    • Northbridge 2 is offline
    • IOMMU is disabled
  • SeaBIOS + uCode + VGA-OpROMs

H8DGi-F

The H8DGi-F is identical to the H8DGi, but has an onboard BMC. It is compatible with the coreboot image for the H8DGi, but it is not known whether the onboard BMC will operate. The "JPB1" motherboard jumper can be used to disable the onboard BMC, effectively turning the H8DGi-F into the H8DGi.

H8DG6

The H8DG6 has an onboard SAS controller; it can be flashed to IT mode.

Release
Notes
Download Options
2025.05.08-v4.11-7f9e8d15532
  • Initial support
    • Onboard SAS enabled
    • No fan control
    • Northbridge 2 is offline
    • IOMMU is disabled
  • SeaBIOS + uCode + VGA-OpROMs

H8DG6-F

The H8DG6-F is identical to the H8DG6, but has an onboard BMC. It is compatible with the coreboot image for the H8DG6, but it is not known whether the onboard BMC will operate. The "JPB1" motherboard jumper can be used to disable the onboard BMC, effectively turning the H8DG6-F into the H8DG6.

Board Diagrams

Board Components

Socket G34

G34 socket pinout

G34 was launched on March 29, 2010. It supports 10h and 15h CPU's[1]. It is a dual node CPU.

AMD Opteron 6100 Series

Processors in the AMD Opteron 6100 Series were designed with the K10 microarchitecture and are compatible with the G34 socket.

Official Source Code and Documentation

AMD Opteron 6200 and 6300 Series

Processors in the AMD Opteron 6200 and 6300 Series were designed with the Bulldozer (6200 series) and Piledriver (6300 series) microarchitectures and are compatible with the G34 socket.

Official Source Code and Documentation

AMD SR5690

The AMD SR5690, also known as RD890S, was released in March 2010 as a powerful system logic for server and workstation platforms. It offers 46 PCI Express lanes, with 42 lanes dedicated to external PCIe devices and 4 for the A-Link Express II interface to AMD's Southbridges like the SP5100 (formerly SB700S). The chipset boasts the latest technologies, including HyperTransport™ 3 and PCIe Gen 2, and its highly integrated, thermally efficient design comes in a compact 29mm x 29mm package.[2]

Official Source Code and Documentation

AMD SP5100

The AMD SP5100 is a versatile Southbridge designed to complement AMD's server Northbridges, integrating essential I/O, communication, and other features for advanced server platforms into a single device. [3]

Official Source Code and Documentation

Nuvoton WPCM450

The Nuvoton WPCM450, or simply the WPCM450, is a BMC chip used in the SuperMicro family of boards containing the "-F" suffix. Multiple vendors shipped the WPCM450 with Linux, making it feasible to build an open source replacement for the original BMC firmware[4][5][6]. 3rd party documentation and tools have been developed by neuschaefer and are available on github.

Missing Features

  • Support for the W83795 is incomplete (no fan control).
  • Support for the secondary SR5690 has not been implemented (PCIe slots 1, 2, and 4 are offline).
  • Support for the SR5690 IOMMU has not been implemented.

Flashing Firmware

To switch from the stock firmware to coreboot, external flashing is required. The stock BIOS chip is a 2 MiB SOIC8 located below PCIe slot 2, next to the NVRAM battery.

User Builds

References

  1. ↑ https://en.wikipedia.org/wiki/Socket_G34
  2. ↑ https://theretroweb.com/chips/5696
  3. ↑ https://theretroweb.com/chips/5699
  4. ↑ https://github.com/neuschaefer/linux/tree/vendor/wpcm450-aten
  5. ↑ https://github.com/neuschaefer/linux/tree/vendor/wpcm450-ami
  6. ↑ https://github.com/neuschaefer/linux/tree/vendor/dell-idrac6-1.70
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